The present invention relates to a vertical transistor and a method for forming the same, and more particularly, to a vertical transistor which can prevent a floating body effect and improve the characteristics of the vertical transistor and a method for forming the same.
In general, various manufacturing technologies are employed in a method for forming transistors and bit lines in a semiconductor device. These days, a MOSFET (metal oxide semiconductor field effect transistor) for producing a field effect by forming an oxide layer on a semiconductor substrate has been highlighted in the art.
In the MOSFET, processes are adopted to form transistors in the regions of the semiconductor substrate which are divided into a cell region and a peripheral circuit region. The transistors are formed by depositing a gate insulation layer and a gate conductive layer on the semiconductor substrate. The gate conductive layer is usually made of a polysilicon layer or the stack of a polysilicon layer and a metal-based layer.
Meanwhile, as the design rule of a semiconductor device decreases, the recent semiconductor industry trends toward increasing the integration level, the operation speed and the yield of a semiconductor device. In conformity with this trend, in order to overcome the limitations of a conventional transistor, regarding the integration level and the current performance of a semiconductor device, a vertical transistor has been suggested.
Differently from a conventional vertical transistor composed of a gate and source and drain regions which are formed in a semiconductor substrate on both sides of the gate so that a horizontal channel is defined, the vertical transistor is composed of a gate and source and drain regions which are formed over and under the gate so that a vertical channel is defined.
The channel of the vertical transistor is electrically connected with the semiconductor substrate through a portion of the semiconductor substrate which is positioned between the source regions. Through this, a body voltage can be applied to the vertical transistor.
However, in the conventional vertical transistor described above, as the design rule of a semiconductor device decreases, the interval between the neighboring source regions also decreases. Due to the decrease in the interval between the neighboring source regions, the impurities of the source regions may diffuse so that the interval between the source regions vanishes.
If the interval between the source regions vanishes, the body voltage applied from the semiconductor substrate may not be transmitted to the channel of the vertical transistor. Due to this fact, as the body of the vertical transistor for storing charges is floated, various problems are caused.
Concretely speaking, the electrical path between the vertical transistor and the semiconductor substrate is blocked by the presence of the source regions, and therefore, body bias cannot be applied to the channel of the vertical transistor. As a result, since the charges accumulated in the body of the vertical transistor cannot be discharged to the semiconductor substrate, the floating body effect is caused.
The floating body effects indicates a phenomenon that gate induced drain leakage (GIDL) or hot carrier injection occurs in an NMOS transistor, holes are trapped in the channel, and the threshold voltage of the transistor decreases due to the presence of the holes.
Therefore, in the conventional art, it is difficult to properly control the transistor due to the floating body effect, as a result of which the characteristics of the transistor are likely to be degraded.